View SAA5288_113416.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
DATA SHEET
SAA5288 TV microcontroller with full screen On Screen Display (OSD)
Preliminary specification File under Integrated Circuits, IC02 1997 Jun 24
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
CONTENTS 1 1.1 1.2 1.3 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.4 7.4.1 7.4.2 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.6 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.7 7.8 FEATURES General Microcontroller Display GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pinning Pin description FUNCTIONAL DESCRIPTION Microcontroller 80C51 features not supported Interrupt priority Off-chip memory Idle and Power-down modes UART function Additional features Interrupts Bit Level I2C-bus Interface Byte Level I2C-bus Interface LED support 6-bit PWM DACs 14-bit PWM DAC Software ADC Microcontroller Interfacing Special Function Register map Special Function Registers bit description The display Introduction Character matrix Page attributes East/west selection National option characters The twist attribute On screen display symbols Language group identification 525-line operation Control characters Display modes On Screen Display boxes Screen colour 7.9 7.10 7.11 7.12 7.13 7.14 7.15 8 8.1 8.2 8.3 8.4 8.5 8.6 9 10 11 12 13 14 15 16 16.1 16.2 16.3 17 18 19 Cursor Other display features Display timing Horizontal timing Vertical timing Display position Clock generator CHARACTER SETS Pan-European Russian Greek/Turkish Arabic/English/French Thai Arabic/Hebrew LIMITING VALUES CHARACTERISTICS
SAA5288
CHARACTERISTICS FOR THE I2C-BUS INTERFACE QUALITY SPECIFICATIONS APPLICATION INFORMATION EMC GUIDELINES PACKAGE OUTLINE SOLDERING Introduction Soldering by dipping or by wave Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1997 Jun 24
2
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
1 1.1 FEATURES General
SAA5288
* 260 characters in mask programmed ROM * Display clock derived internally to reduce peripheral components to a minimum * Automatic FRAME output control with manual override * Standby mode for display hardware * 525-line and 625-line display * 12 x 10 character matrix * Stable Display via slave synchronization to Horizontal Sync and Vertical Sync. 2 GENERAL DESCRIPTION
* On-chip TV control tuning * Hardware and software compatible with SAA5290, SAA5291 and SAA5296 * Single +5 V power supply * RGB interface to standard decoder ICs, push-pull output drive * SDIP52 package * Single crystal oscillator for display and microcontroller. 1.2 Microcontroller
* 80C51 microcontroller core * 16 kbyte mask programmed ROM * 256 bytes of microcontroller RAM * Eight 6-bit Pulse Width Modulator (PWM) outputs for control of TV analog signals * One 14-bit PWM for Voltage Synthesis tuner control * Four 8-bit Analog-to-Digital Converters (ADCs) * 2 high current open-drain outputs for directly driving LED's etc. * Switchable bit or byte-oriented 1.3 Display I2C-bus interface.
The SAA5288 is a microcontroller for use in televisions with an OSD generator compatible with the Economy Teletext/TV microcontroller family (SAA5290, SAA5291, SAA5296 etc.). TV control facilities are provided by an on-chip industry standard 80C51 microcontroller and a 1 kbyte DRAM is included for OSD memory. Hardware and software compatibility with the Economy Teletext/TV microcontroller family minimizes the changes required to develop a TV control function for areas where teletext is not broadcast. The device cannot acquire Teletext but is based on a Teletext device. Therefore, throughout this document references are made to Teletext especially when describing the Display/OSD section. The Display/OSD section is fully compatible with a Teletext display and has all the features associated with Teletext (i.e. double height/width, flash, teletext boxes, graphics, etc.). The Display section is described with reference to Teletext to allow software compatibility with the Economy Teletext/TV microcontroller family.
* Single page (1024 x 8) on-board On Screen Display (OSD) memory * Double size width and height capability for OSD * Enhanced display features including meshing, shadowing and additional display attributes 3 QUICK REFERENCE DATA SYMBOL VDD IDDM IDDA IDDT fxtal Tamb PARAMETER supply voltage (all supplies) microcontroller supply current analogue supply current display supply current crystal frequency operating ambient temperature
MIN. 4.5 - - - - -20
TYP. 5.0 15 8 15 12 -
MAX. 5.5 30 15 30 - +70 V
UNIT mA mA mA MHz
C
1997 Jun 24
3
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA5288PS/nnn 5 SDIP52 DESCRIPTION plastic shrink dual in-line package; 52 leads (600 mil)
SAA5288
VERSION SOT247-1
BLOCK DIAGRAM
handbook, full pagewidth VDDA
VDDD VDDM
VSSD
XTALIN XTALOUT OSCGND
DISPLAY OSCILLATOR PAGE RAM
R, G, B, VDS, COR VSYNC HSYNC FRAME
DISPLAY TIMING
16 KBYTE ROM data 8051 CPU address
256 BYTE RAM
TEXT INTERFACE
RESET
I2C-BUS interrupt TIMER/ COUNTER ADC PWM
PORT 1
PORT 0
PORT 3
PORT 2
MGL121
P1.0 to P1.7
P0.0 to P0.7
P3.0 to P3.7
P2.0 to P2.7
Fig.1 Block diagram.
1997 Jun 24
4
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
6 6.1 PINNING INFORMATION Pinning
SAA5288
handbook, halfpage
P2.0/TPWM 1 P2.1/PWM0 2 P2.2/PWM1 3 P2.3/PWM2 4 P2.4/PWM3 5 P2.5/PWM4 6 P2.6/PWM5 7 P2.7/PWM6 8 P3.0/ADC0 9 P3.1/ADC1 10 P3.2/ADC2 11 P3.3/ADC3 12 VSSD 13 P0.0 14 P0.1 15 P0.2 16 P0.3 17 P0.4 18 P0.5 19 P0.6 20 P0.7 21 VSSD 22 i.c. 23 i.c. 24 i.c. 25 IREF 26
MGL114
52 P1.5 51 P1.4 50 P1.7/SDA 49 P1.6/SCL 48 P1.3/T1 47 P1.2/INT0 46 P1.1/T0 45 P1.0/INT 44 VDDM 43 RESET 42 XTALOUT 41 XTALIN 40 OSCGND
SAA5288
39 VDDD 38 VDDA 37 VSYNC 36 HSYNC 35 VDS 34 R 33 G 32 B 31 RGBREF 30 P3.4/PWM7 29 COR 28 VSSD 27 FRAME
Fig.2 Pin configuration.
1997 Jun 24
5
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
6.2 Pin description SDIP52 package PIN 1 2 3 4 5 6 7 8 9 10 11 12 30 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Digital ground. Internally connected; this pin should be connected to digital ground. Internally connected; this pin should be connected to digital ground. Internally connected; this pin should be connected to digital ground. Digital ground Port 0. 8-bit open-drain bidirectional port. Port 3. 8-bit open-drain bidirectional port with alternative functions. DESCRIPTION Port 2. 8-bit open-drain bidirectional port with alternative functions. P2.0/TPWM is the output for the 14-bit high precision PWM.
SAA5288
Table 1
SYMBOL P2.0/TPWM P2.1/PWM0 P2.2/PWM1 P2.3/PWM2 P2.4/PWM3 P2.5/PWM4 P2.6/PWM5 P2.7/PWM6 P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 P3.4/PWM7 VSSD P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 VSSD i.c. i.c. i.c. IREF
P2.1/PWM0 to P2.7/PWM6 are the outputs for the 6-bit PWMs 0 to 6.
P3.0/ADC0 to P3.3/ADC3 are the inputs for the software ADC facility. P3.4/PWM7 is the output for the 6-bit PWM7.
P0.5 and P0.6 have 10 mA current sinking capability for direct drive of LEDs.
Reference current input for analog current generator, connected to VSSA via a 27 k resistor.
1997 Jun 24
6
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
SYMBOL FRAME VSSD COR RGBREF B G R VDS HSYNC VSYNC VDDA VDDD OSCGND XTALIN XTALOUT RESET PIN 27 28 29 31 32 33 34 35 36 37 38 39 40 41 42 43 DESCRIPTION
SAA5288
De-interlace output synchronised with the VSYNC pulse to produce a non-interlaced display by adjustment of the vertical deflection circuits. Internally connected; this pin should be connected to digital ground. Open-drain, active LOW output which allows selective contrast reduction of the TV picture to enhance a mixed mode display. DC input voltage to define the output HIGH level on the RGB pins. Pixel rate output of the BLUE colour information. Pixel rate output of the GREEN colour information. Pixel rate output of the RED colour information. Video/data switch push-pull output for dot rate fast blanking. Schmitt trigger input for a TTL level version of the horizontal sync pulse; the polarity of this pulse is programmable by register bit TXT1.H POLARITY. Schmitt trigger input for a TTL level version of the vertical sync pulse; the polarity of this pulse is programmable by register bit TXT1.V POLARITY. +5 V display power supply. +5 V display power supply. Crystal oscillator ground. 12 MHz crystal oscillator input. 12 MHz crystal oscillator output. If the reset input is HIGH for at least 3 machine cycles (36 oscillator periods) while the oscillator is running, the device is reset; this pin should be connected to VDDM via a 2.2 F capacitor. +5 V microcontroller power supply. Port 1. 8-bit open-drain bidirectional port with alternative functions. P1.0/INT1 is external interrupt 1, can be triggered on the rising/falling edge of pulse. P1.1/T0 is the counter/timer 0. P1.2/INT0 is the external interrupt 0. P1.3/T1 is the counter/timer 1. P1.7/SDA is the serial data port for the I2C-bus. P1.6/SCL is the serial clock input for the I2C-bus.
VDDM P1.0/INT1 P1.1/T0 P1.2/INT0 P1.3/INT1 P1.6/SCL P1.7/SDA P1.4 P1.5
44 45 46 47 48 49 50 51 52
1997 Jun 24
7
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
7 7.1 FUNCTIONAL DESCRIPTION Microcontroller 7.3 Additional features
SAA5288
The functionality of the microcontroller used with this family is described with reference to the industry-standard 80C51 microcontroller. A full description of its functionality can be found in "80C51-Based; 8-bit Microcontrollers, Data Handbook IC20". Using the 80C51 as a reference, the changes made to this family fall into two categories: * Features not supported by the SAA5288 * Features found on the SAA5288 but not supported by the 80C51. 7.2 7.2.1 80C51 features not supported INTERRUPT PRIORITY
The following features are provided in addition to the standard 80C51 features. 7.3.1 INTERRUPTS
The external INT1 interrupt is modified to generate an interrupt on both the rising and falling edges of the INT1 pin, when EX1 bit is set. This facility allows for software pulse-width measurement for handling of a remote control. 7.3.2 BIT LEVEL I2C-BUS INTERFACE
The IP SFR is not implemented and all interrupts are treated with the same priority level. The normal priority of interrupts is maintained within the level. Table 2 Interrupts and vector address VECTOR ADDRESS (HEX) 000 003 00B 013 01B 02B 053
For reasons of compatibility with the SAA5290, SAA5291, SAA5291A and SAA5491 all contain a bit level serial I/O which supports the I2C-bus. P1.6/SCL and P1.7/SDA are the serial I/O pins. These two pins meet the I2C-bus specification concerning the input levels and output drive capability see "The I2C-bus and how to use it (including specifications)". Consequently, these two pins have an open-drain output configuration. All the four following modes of the I2C-bus are supported. * Master transmitter * Master receiver * Slave transmitter * Slave receiver. Three SFRs support the function of the bit-level I2C-bus hardware: S1INT, S1BIT and S1SCS and are enabled by setting register bit TXT8.I2C SELECT to logic 0. 7.3.3 BYTE LEVEL I2C-BUS INTERFACE
INTERRUPT SOURCE Reset External INT0 Timer 0 External INT1 Timer 1 Byte I2C-bus Bit I2C-bus OFF-CHIP MEMORY
7.2.2
The SAA5288 does not support the use of off-chip program memory or off-chip data memory. 7.2.3 IDLE AND POWER-DOWN MODES
The byte level serial I/O supports the I2C-bus protocol. P1.6/SCL and P1.7/SDA are the serial I/O pins. These two pins meet the I2C-bus specification concerning the input levels and output drive capability. Consequently, these two pins have an open-drain output configuration. The byte level I2C-bus serial port is identical to the I2C-bus serial port on the 8xC552. The operation of the subsystem is described in detail in the 8xC552 data sheet described in "80C51-Based; 8-bit Microcontrollers Data Handbook IC20". Four SFRs support the byte level I2C-bus hardware: S1CON, S1STA, S1DAT and S1ADR. They are enabled by setting register bit TXT8. I2C SELECT to logic 1. 7.3.4 LED SUPPORT
Idle and Power-down modes are not supported. Consequently, the respective bits in PCON are not available. 7.2.4 UART FUNCTION
The 80C51 UART is not available. As a consequence the SCON and SBUF SFRs are removed and the ES bit in the IE SFR is unavailable.
Port pins P0.5 and P0.6 have a 10 mA current sinking capability to enable LEDs to be driven directly.
1997 Jun 24
8
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
7.3.5 6-BIT PWM DACS
SAA5288
Eight 6-bit DACs are available to allow direct control of analogue sections of the television. Each low resolution 6-bit DAC is controlled by its associated Special Function Register (PWM0 to PWM7). The PWM outputs are alternative functions of Port 2 and P3.4. The PWE bit in the SFR for the port corresponding to the PWM should be set to logic 1 for correct operation of the PWM, e.g. if PWM0 is to be used, P2.1 should be set to logic 1 setting the port pin to high-impedance.
7.3.5.1
Table 3 7 PWE Table 4 BIT 7
Pulse Width Modulator Registers (PWM0 to PWM7)
Pulse Width Modulator Registers (see Table 10 for addresses) 6 - 5 PV5 4 PV4 3 PV3 2 PV2 1 PV1 0 PV0
Description of PWMn bits (n = 0 to 7) SYMBOL PWE DESCRIPTION If PWE is set to a logic 1, the corresponding PWM is active and controls its assigned port pin. If PWE is set to la logic 0, the port pin is controlled by the corresponding bit in the port SFR. not used The output of the PWM is a pulse of period 21.33 s with a pulse HIGH time determined by the binary value of these 6-bits multiplied by 0.33 s. PV5 is the most significant bit.
6 5 4 3 2 1 0
- PV5 PV4 PV3 PV2 PV1 PV0
1997 Jun 24
9
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
7.3.6 14-BIT PWM DAC
SAA5288
One 14-bit DAC is available to allow direct control of analogue sections of the television. The 14-bit PWM is controlled using Special Function Registers TDACL and TDACH. The output of the TPWM is a pulse of period 42.66 s. The 7 most significant bits, TDACH.TD13 (MSB) to TDACH.TD8 and TDACL.TD7, alter the pulse width between 0 and 42.33 s, in much the same way as in the 6-bit PWMs. The 7 least significant bits, TDACL.TD6 to TDACL.TD0 (LSB), extend certain pulses by a further 0.33 s, e.g. if the 7 least significant bits are given the value 01H, then 1 in 128 cycles is extended. If the 7 least significant bits are given the value 02H, then 2 in 128 cycles is extended, and so forth. The TPWM will not start to output a new value until after writing a value to TDACH. Therefore, if the value is to be changed, TDACL should be written to before TDACH.
7.3.6.1
Table 5 7 PWE Table 6 BIT 7 6 5 4 3 2 1 0
TPWM High Byte Register (TDACH)
TPWM High Byte Register (SFR address D3H) 6 - 5 TD13 4 TD12 3 TD11 2 TD10 1 TD9 0 TD8
Description of TDACH bits SYMBOL PWE - TD13 TD12 TD11 TD10 TD9 TD8 DESCRIPTION If PWE is set to a logic 1, the TPWM is active and controls port line P2.0. If PWE is set to a logic 0, the port pin is controlled by the corresponding bit in the port SFR. not used These 6-bits along with bit TD7 in the TDACL register control the pulse width period. TD13 is the most significant bit.
7.3.6.2
Table 7 7 TD7 Table 8 BIT 7 6 to 0
TPWM Low Byte Register (TDACL)
TPWM Low Byte Register (SFR address D2H) 6 TD6 5 TD5 4 TD4 3 TD3 2 TD2 1 TD1 0 TD0
Description of TDACL bits SYMBOL TD7 TD6 to TD0 DESCRIPTION This bit is used with bits TD13 to TD8 in the TDACH register to control the pulse width period. These 7-bits extend certain pulses by a further 0.33 s.
1997 Jun 24
10
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
7.3.7 SOFTWARE ADC
SAA5288
The control of the ADC is achieved using the Special Function Registers SAD and SADB. SAD.CH1 and SAD.CH0 select one of the four inputs to pass to the comparator. The other comparator input comes from the DAC, whose value is set by SAD.SAD7 (MSB) to SAD.SAD4 and SADB.SAD3 to SADB.SAD0 (LSB). The setting of the value SAD.SAD7 to SAD.SAD4 must be performed at least 1 instruction cycle before the setting of SAD.ST to ensure comparison is made using the correct SAD.SAD7 to SAD.SAD4 value. The output of the comparator is SAD.VHI, and is valid after 1 instruction cycle following the setting of SAD.ST to logic 1.
Up to 4 successive approximation ADCs can be implemented in software by making use of the on-chip 8-bit DAC and multiplexed voltage comparator. The software ADC uses 4 analog inputs which are multiplexed with P3.0 to P3.3. Table 9 ADC input channel selection CH0 0 1 0 1 INPUT PIN P3.3/ADC3 P3.0/ADC0 P3.1/ADC1 P3.2/ADC2
CH1 0 0 1 1
handbook, halfpage
P3.0 P3.1
ST
C1 1D VH1
MULTIPLEXER P3.2 P3.3 8-BIT DAC CH1, CH0 REF- REF+
SAD7 to SAD0
MGL115
Fig.3 SAD block diagram.
1997 Jun 24
11
1997 Jun 24 12
Philips Semiconductors
7.4
Microcontroller Interfacing
TV microcontroller with full screen On Screen Display (OSD)
The 80C51 communicates with the peripheral functions using Special Function Registers which are addressed as RAM locations. The registers in the teletext decoder appear as normal SFRs in the microcontroller memory map, but are written to using an internal serial bus. The SFR map is given in Section 7.4.1 and the SFR bit description is given in Section 7.4.2. 7.4.1 SPECIAL FUNCTION REGISTER MAP
Table 10 Special Function Register map; note 1
SYMBOL ACC(2) B(2) DPTR: DPH DPL IE(2)(3) P0(2) P1(2) P2(2) P3(2)(3) PCON(3) PSW(2) NAME Accumulator B register Data Pointer (2 bytes): High byte Low byte Interrupt Enable Port 0 Port 1 Port 2 Port 3 Power Control Program Status Word 83 82 A8 80 90 A0 B0 87 D0 - - AF EA 87 - 97 - A7 - - - - D7 CY - - AE ES1 86 - 96 - A6 - - - * D6 AC - - AD ES2 85 - 95 - A5 - - - - D5 F0 - - AC * 84 - 94 - A4 - - - * D4 RS1 - - AB ET1 83 - 93 - A3 - B3 - GF1 D3 RS0 - - AA EX1 82 - 92 - A2 - B2 - GF0 D2 OV - - A9 ET0 81 - 91 - A1 - B1 - - D1 * - - A8 EX0 80 - 90 - A0 - B0 - - D0 P 10 00 FF FF FF FF 00 00 00 DIRECT ADDRESS (HEX) E0 F0 BIT ADDRESS, SYMBOL OR ALTERNATIVE PORT FUNCTION 7 E7 - F7 - 6 E6 - F6 - 5 E5 - F5 - 4 E4 - F4 - 3 E3 - F3 - 2 E2 - F2 - 1 E1 - F1 - 0 E0 - F0 - 00 RESET VALUE (HEX) 00
Preliminary specification
SAA5288
1997 Jun 24 13
Philips Semiconductors
SYMBOL PWM0(3) PWM1(3) PWM2(3) PWM3(3) PWM4(3) PWM5(3) PWM6(3) PWM7(3) S1ADR(3) S1CON
(2)(3)(4)
NAME Pulse Width Modulator 0 Pulse Width Modulator 1 Pulse Width Modulator 2 Pulse Width Modulator 3 Pulse Width Modulator 4 Pulse Width Modulator 5 Pulse Width Modulator 6 Pulse Width Modulator 7 Serial I2C-bus address Serial I2C-bus control Serial control Serial data I2C-bus I2C-bus
DIRECT ADDRESS (HEX) D5 D6 D7 DC DD DE DF D4 DB D8 D8 DA DA D9 D9
BIT ADDRESS, SYMBOL OR ALTERNATIVE PORT FUNCTION 7 PWE PWE PWE PWE PWE PWE PWE PWE ADR6 DF CR2 DF SDI DAT7 SI STAT4 SDO/SDI 6 * * * * * * * * ADR5 DE ENSI DE SCI DAT6 - STAT3 - 5 PV5 PV5 PV5 PV5 PV5 PV5 PV5 PV5 ADR4 DD STA DD CLH DAT5 - STAT2 - 4 PV4 PV4 PV4 PV4 PV4 PV4 PV4 PV4 ADR3 DC STO DC BB DAT4 - STAT1 - 3 PV3 PV3 PV3 PV3 PV3 PV3 PV3 PV3 ADR2 DB SI DB RBF DAT3 - STAT0 - 2 PV2 PV2 PV2 PV2 PV2 PV2 PV2 PV2 ADR1 DA AA DA WBF DAT2 - 0 - 1 PV1 PV1 PV1 PV1 PV1 PV1 PV1 PV1 ADR0 D9 CR1 D9 STR DAT1 - 0 - 0 PV0 PV0 PV0 PV0 PV0 PV0 PV0 PV0 GC D8 CR0 D8 ENS DAT0 - 0 -
RESET VALUE (HEX) 40 40 40 40 40 40 40 40 00
TV microcontroller with full screen On Screen Display (OSD)
00 E0 00 7F F8 7F
S1SCS
(2)(3)(5)
S1DAT
(3)(4)
S1INT
(3)(5)
Serial I2C-bus Interrupt Serial I2C-bus status Serial I2C-bus data
S1STA
(3)(4)
Preliminary specification
S1BIT
(3)(5)
SAA5288
1997 Jun 24 14
Philips Semiconductors
SYMBOL SAD(2)(3) SADB
(2)(3)
NAME Software ADC (MSB) Software ADC (LSB) Stack Pointer Timer/counter control TPWM High byte TPWM Low byte Timer 0 High byte Timer 1 High byte Timer 0 Low byte Timer 1 Low byte Timer/counter mode Teletext Register 0
DIRECT ADDRESS (HEX) E8 98 81 88 D3 D2 8C 8D 8A 8B 89 C0
BIT ADDRESS, SYMBOL OR ALTERNATIVE PORT FUNCTION 7 EF VHI 9F - 8F TF1 PWE TD7 TH07 TH17 TL07 TL17 GATE * 6 EE CH1 9E - 8E TR1 * TD6 TH06 TH16 TL06 TL16 C/T Timer 1 * AUTO FRAME * DISPLAY STATUS ROW ONLY * B MESH ENABLE TEXT OUT 5 ED CH0 9D - 8D TF0 TD13 TD5 TH05 TH15 TL05 TL15 M1 4 EC ST 9C - 8C TR0 TD12 TD4 TH04 TH14 TL04 TL14 M0 3 EB SAD7 9B SAD3 8B IE1 TD11 TD3 TH03 TH13 TL03 TL13 GATE 2 EA SAD6 9A SAD2 8A IT1 TD10 TD2 TH02 TH12 TL02 TL12 C/T Timer 0 DISABLE FRAME * * 1 E9 SAD5 99 SAD1 89 IE0 TD9 TD1 TH01 TH11 TL01 TL11 M1 0 E8 SAD4 98 SAD0 88 IT0 TD8 TD0 TH00 TH10 TL00 TL10 M0
RESET VALUE (HEX) 00 00 07 00 40 00 00 00 00 00 00 00
TV microcontroller with full screen On Screen Display (OSD)
SP TCON(2) TDACH TDACL TH0 TH1 TL0 TL1 TMOD TXT0(3)
TXT1(3) TXT4(3) TXT5(3)
Teletext Register 1 Teletext Register 4 Teletext Register 5
C1 C4 C5
* * BKGND OUT
* * BKGND IN
* EAST/ WEST COR OUT
* DISABLE DBL HT COR IN
FIELD H V POLARITY POLARITY POLARITY C MESH ENABLE TEXT IN TRANS ENABLE PICTURE ON OUT SHADOW ENABLE PICTURE ON IN
00
Preliminary specification
00
SAA5288
03
1997 Jun 24 15
Philips Semiconductors
SYMBOL TXT6(3) TXT7(3)
NAME Teletext Register 6 Teletext Register 7 Teletext Register 8 Teletext Register 9 Teletext Register 10 Teletext Register 11 Teletext Register 12 Teletext Register 13 Teletext Register 16 Teletext Register 17
DIRECT ADDRESS (HEX) C6 C7
BIT ADDRESS, SYMBOL OR ALTERNATIVE PORT FUNCTION 7 BKGND OUT STATUS ROW TOP I2C SELECT CURSOR FREEZE * D7 * BF * 6 BKGND IN CURSOR ON * CLEAR MEMORY * D6 ROM VER R4 BE 5 COR OUT REVEAL 4 COR IN TOP/ BOTTOM * R4 C4 D4 ROM VER R2 BC * Y0 FORCE 625 3 TEXT OUT DOUBLE HEIGHT * R3 C3 D3 ROM VER R1 BB * * FORCE 525 2 TEXT IN BOX ON 24 * R2 C2 D2 ROM VER R0 BA * * SCREEN COL2 1 PICTURE ON OUT BOX ON 1-23 * R1 C1 D1 TXT ON B9 * X1 SCREEN COL1 0 PICTURE ON IN BOX ON 0 * R0 C0 D0 * B8 OSD I/F busy X0 SCREEN COL0
RESET VALUE (HEX) 03 00
TV microcontroller with full screen On Screen Display (OSD)
TXT8(3) TXT9(3) TXT10(3) TXT11(3) TXT12(3) TXT13
(2)(3)
C8 C9 CA CB CC B8
* * C5 D5 ROM VER R3 BD
00 00 00 00 0XXXX X00B 00
PAGE 525 CLEARING DISPLAY Y2 * Y1 *
TXT16(3) TXT17(3)
CF B9
* *
00 00
Notes 1. The asterisk (*) indicates these bits are inactive and must be written to logic 0 for future compatibility. 2. SFRs are bit addressable. 3. SFRs are modified or added to the 80C51 SFRs. Preliminary specification 4. This register is used for Byte Orientated I2C-bus, TXT8. I2C SELECT = 1. 5. This register is used for Bit Orientated I2C-bus, TXT8. I2C SELECT = 0.
SAA5288
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
7.4.2 SPECIAL FUNCTION REGISTERS BIT DESCRIPTION
SAA5288
Table 11 SFR bit descriptions REGISTER Interrupt Enable Register (IE) EA ES1 ES2 ET1 EX1 ET0 EX0 disable all interrupts (logic 0) or use individual interrupt enable bits (logic 1) bit I2C-bus interrupt enable (logic 1) byte I2C-bus interrupt enable (logic 1) enable Timer 1 overflow interrupt (logic 1) enable external interrupt 1 (logic 1) enable Timer 0 overflow interrupt (logic 1) enable external interrupt 0 (logic 1) FUNCTION
Power Control Register (PCON) GF1 GF0 general purpose flag 1 general purpose flag 0
Program Status Word (PSW) CY AC F0 RS1, RS0 OV P carry flag auxiliary carry flag flag 0 register bank select control bits overflow flag parity flag
6-bit Pulse Width Modulator Control Registers (PWM0 to PWM7) PWE PV5 to PV0 activate this PWM and take control of respective port pin (logic 1) binary value sets high time of PWM output I2C-bus slave address to which the device will respond enables response to the I2C-bus general call address
Serial Interface Slave Address Register (S1ADR) ADR6 to ADR0 GC
Serial Interface Control Register (S1CON) CR2 to CR0 ENSI STA STO SI AA clock rate bits I2C-bus interface enable start condition flag stop condition flag interrupt flag assert acknowledge flag
1997 Jun 24
16
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
REGISTER Serial Interface Data Register (S1DAT) DAT7 to DAT0 I2C-bus data I2C-bus interface status I2C-bus data bit input I2C-bus data bit output I2C-bus interrupt flag FUNCTION
SAA5288
Serial Interface Status Register (S1STA) - READ only STAT4 to STAT0
Serial Interface Data Register (S1BIT) - READ SDI
Serial Interface Data Register (S1BIT) - WRITE SDO
Serial Interface Interrupt Register (S1INT) SI
Serial Interface Control Register (S1SCS) - READ SDI SCI CLH BB RBF WBF STR ENS serial data input at SDA serial clock input at SCL clock LOW-to-HIGH transition flag bus busy flag read bit finished flag write bit finished flag clock stretching enable (logic 1) enable serial I/O (logic 1)
Serial Interface Control Register (S1SCS) - WRITE SDO SCO CLH STR ENS serial data output at SDA serial clock output at SCL clock LOW-to-HIGH transition flag clock stretching enable (logic 1) enable serial I/O (logic 1)
Software ADC Control Register (SAD) VHI CH1 and CH0 ST SAD7 to SAD4 comparator output indicating that analogue input voltage greater than DAC voltage (logic 1) ADC input channel selection bits, see Table 11 initiate voltage comparison (logic 1); this bit is automatically reset to logic 0 4 MSB's of DAC input value
Software ADC Control Register (SADB) SAD3 to SAD0 4 LSB's of DAC input value
1997 Jun 24
17
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
REGISTER Timer/Counter Control Register (TCON) TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Timer 1 overflow flag Timer 1 run control bit Timer 0 overflow flag Timer 0 run control bit Interrupt 1 edge flag Interrupt 1 type control bit Interrupt 0 edge flag Interrupt 0 type control bit FUNCTION
SAA5288
14-bit PWM MSB Register (TDACH) PWE TD13 to TD8 activate this 14-bit PWM and take over port pin (logic 1) 6 MSBs of 14-bit number to be output by the 14-bit PWM
14-bit PWM LSB Register (TDACL) TD7 to TD0 8 LSBs of 14-bit number to be output by the 14-bit PWM
Timer 0 High byte (TH0) TH07 to TH00 8 MSBs of Timer 0 16-bit counter
Timer 1 High byte (TH1) TH17 to TH10 8 MSBs of Timer 1 16-bit counter
Timer 0 Low byte (TL0) TL07 to TL00 8 LSBs of Timer 0 16-bit counter
Timer 1 Low byte (TL1) TL17 to TL10 8 LSBs of Timer 1 16-bit counter
Timer/Counter Mode Control Register (TMOD) GATE C/T M1, M0 gating control counter or timer selector mode control bits
Teletext Register 0 (TXT0) - WRITE only AUTO FRAME DISPLAY STATUS ROW ONLY DISABLE FRAME FRAME output switched off automatically if any video displayed (logic 1) display row 24 only (logic 1) FRAME output always low (logic 1)
1997 Jun 24
18
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
REGISTER Teletext Register 1 (TXT1) - WRITE only FIELD POLARITY H POLARITY V POLARITY PRD4 to PRD0 FUNCTION
SAA5288
VSYNC in first half of the line (logic 0) or second half of the line (logic 1) at start of even field HSYNC input positive-going (logic 0) or negative-going (logic 1) VSYNC input positive-going (logic 0) or negative-going (logic 1) page request data
Teletext Register 4 (TXT4) - WRITE only EAST/ WEST B MESH ENABLE C MESH ENABLE TRANS ENABLE SHADOW ENABLE western languages selected (logic 0) or Eastern languages selected (logic 1) enable meshing of area with black background (logic 1) enable meshing of area with other background colours (logic 1) set black background to transparent i.e. video is displayed (logic 1) enable south-east shadowing (logic 1) DISABLE DBL HGHT disable display of double height teletext control codes (logic 1) in OSD boxes
Teletext Register 5 (TXT5) - WRITE only BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PICTURE ON OUT PICTURE ON IN background colour displayed outside teletext boxes (logic 1) background colour displayed inside teletext boxes (logic 1) COR output active outside teletext boxes (logic 1) COR output active inside teletext boxes (logic 1) text displayed outside teletext boxes (logic 1) text displayed inside teletext boxes (logic 1) video picture displayed outside teletext boxes (logic 1) video picture displayed inside teletext boxes (logic 1)
Teletext Register 6 (TXT6) - WRITE only See TXT5 this register has the same meaning as TXT5 but is only invoked if either newsflash (C5) or subtitle (C6) bit in row 25 of the basic page memory is set
Teletext Register 7 (TXT7) - WRITE only STATUS ROW TOP CURSOR ON REVEAL TOP/BOTTOM DOUBLE HEIGHT BOX ON 24 BOX ON 1-23 BOX ON 0 display row 24 below (logic 0) or above (logic 1) teletext page display cursor at location pointed to by TXT9 and TXT10 (logic 1) display characters in areas with the conceal attribute set (logic 1) display rows 0 to 11 (logic 0) or 12 to 23 (logic 1) when the double height bit is set display each character as twice normal height (logic 1) enable teletext boxes in memory row 24 (logic 1) enable teletext boxes in memory rows 1 to 23 (logic 1) enable teletext boxes in memory row 0 (logic 1)
1997 Jun 24
19
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
REGISTER Teletext Register 8 (TXT8) I2C SELECT select bit I2C-bus (logic 0) or byte I2C-bus (logic 1) FUNCTION
SAA5288
Teletext Register 9 (TXT9) - WRITE only CURSOR FREEZE CLEAR MEMORY R4 to R0 locks current cursor position (logic 1) write 20H into every location in display memory (logic 1) memory row to be accessed by TXT11
Teletext Register 10 (TXT10) - WRITE only C5 to C0 memory column to be accessed by TXT11
Teletext Register 11 (TXT11) D7 to D0 data byte written to, or read from display memory
Teletext Register 12 (TXT12) - READ only ROM VER R4 to R0 DISPLAY ON mask programmable identification for character set power has been applied to the display hardware (logic 1)
Teletext Register 13 (TXT13) PAGE CLEARING 525 DISPLAY OSD I/F Busy set when software requested page clear in progress set to logic 1 when 525-line syncs are driving the display OSD interface busy; logic 1 indicates that TXT Registers 0 to 16 can not currently be accessed
Teletext Register 16 (TXT16) - WRITE only Y2 to Y0 X1 to X0 sets vertical position of display area sets horizontal position of display area
Teletext Register 17 (TXT17) - Write only FORCE 625 FORCE 525 SCREEN COL 2 to 0 force display to 625-line mode force display to 525-line mode defines colour displayed instead of TV picture and black background
1997 Jun 24
20
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
7.5 7.5.1 The display INTRODUCTION 7.5.3 PAGE ATTRIBUTES
SAA5288
The capabilities of the display are based on the requirements of level 1 teletext, with some enhancements for use with locally generated on screen displays. The display consists of 25 rows each of 40 characters, with the characters displayed being those from rows 0 to 24 of the basic page memory. If the TXT.7 STATUS ROW TOP bit is set row 24 is displayed at the top of the screen, followed by row 0, but normally memory rows are displayed in numerical order. The display memory stores 8-bit character codes which correspond to a number of displayable characters and control characters, which are normally displayed as spaces. The character set of the device is described in more detail in Section 8. 7.5.2 CHARACTER MATRIX
Columns 0 to 9 of row 25 of the memory are treated by the display as if they contain display control information from teletext page headers. The bits which affect the display are shown in Table 12. Columns 0 to 4 are not used. If C5 (newsflash) or C6 (subtitle) is set the display uses the display mode defined in register TXT6. C7 (suppress header) causes the header row (row 0) to be displayed as if every character was a space. C10 (inhibit display) displays every character on all rows as if it was a space. C12 to C14 (language control bits) cause certain character codes to be interpreted differently (see Section 7.5.5). Table 12 Page attributes PAGE ATTRIBUTE FIELD COLUMN 7 5 6 7 8 9 0 0 0 0 0 6 0 0 0 0 0 5 0 0 0 0 0 4 0 0 0 0 0 3 C6 C10 C14 0 0 2 C5 0 C13 0 0 1 0 0 C12 0 0 0 0 C7 0 0 0
Each character is defined by a matrix 12 pixels wide and 10 pixels high. When displayed, each pixel is 112 ms wide and 1 TV line, in each field, high.
handbook, full pagewidth
0 DISPLAY PAGE MEMORY ROW 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 page attributes 0 9 23
39
MGL116
Fig.4 Display page organisation.
1997 Jun 24
21
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
7.5.4 EAST/WEST SELECTION 7.6.2
SAA5288
LANGUAGE GROUP IDENTIFICATION
In common with their predecessors, these devices store teletext pages as a series of 8-bit character codes which are interpreted as either control codes (to change colour, invoke flashing etc.) or displayable characters. When the control characters are excluded, this gives an addressable set of 212 characters at any given time. More characters than this were required to give the language coverage required from the first version of the device. The TXT4. East/West bit was introduced to allow the meanings of character codes D0H to FFH to be changed, depending on where in Europe the device was to be used. This bit is still used with the other language variants, although the name East/West may not make much sense. 7.5.5 NATIONAL OPTION CHARACTERS
The devices have a readable register TXT12 which contains a 5-bit identification code TXT12.ROM VER R4 to TXT12.ROM VER R0 which is intended for use in identifying which character set the device is using. 7.6.3 525-LINE OPERATION
When used with 525-line display syncs, the devices modify their displays such that the bottom line is omitted from each character cell. The character sets have been designed to be readable under these circumstances and anyone designing OSD symbols is advised to consider this mode of operation. 7.6.4 CONTROL CHARACTERS
The interpretation of some character codes between 20H and 7FH depends on the C12 to C14 language control bits stored in row 25 of the display page. The interpretation of the C12 to C14 language control bits is dependant on the East/West bit. 7.6 The twist attribute
Character codes 00H to 1FH, B0H to B7H and BCH to BFH are interpreted as control characters which can be used to change the colour of the characters, the background colour, the size of characters, and various other features. All control characters are normally displayed as spaces. The alphanumerics colour control characters (00H to 07H) are used to change colour of the characters displayed. The graphics control characters (10H to 17H) change the colour of the characters and switch the display into a mode where the codes in columns 2, 3, 6 and 7 of the character table (see the character table above) are displayed as the block mosaic characters in columns 2a, 3a, 6a and 7a. The display of mosaics is switched off using one of the alphanumerics colour control characters. The `new background' character (1DH) the background colour of the display sets the background colour equal to the current foreground colour. The `black background' character (1CH) changes the background colour to black independently of the current foreground colour. The background colour control characters in the upper half of the code table (B0H to B7H) are additions to the normal display control characters which allow the background colour to be changed to any colour with a single control character and independently of the foreground colour. The background colour is changed from the position of the background colour control character.
In many of the character sets, the `twist' serial attribute (code 1BH) can be used to switch to an alternative basic character code table, e.g. to change from the Hebrew alphabet to the Arabic alphabet on an Arabic/Hebrew device. For some national option languages the alternative code table is the default, and a twist control character will switch to the first code table. The display hardware on the devices allows one language to invoke the alternative code table by default when the East/West register bit is a logic 0 and another when the bit is a logic 1. In all of the character sets defined so far, the language which invokes the alternative code table is the same for either setting of the East/West bit. 7.6.1 ON SCREEN DISPLAY SYMBOLS
In the character sets, character codes 80H to 9FH are OSD symbols. An editor is available to allow these characters to be redefined by the customer.
1997 Jun 24
22
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
Displayable characters between a `flash' (08H) and a `steady' (09H) control character will flash on and off. Displayable characters between a `conceal display' (18H) character and an alphanumerics or graphics control character are displayed as spaces, unless the TXT7.REVEAL bit is set. The `contiguous graphics' (19H) and `separated graphics' (1AH) characters control the way in which mosaic shapes are displayed. The difference between the two is shown in Fig.5. Control characters encountered between a `hold graphics' (1EH) control character and a `release graphics' (1FH) control character are displayed as the last character displayed in graphics mode, rather than as spaces. From the hold graphics character until the first character displayed in graphics mode the held character is a space. The `start box' (0BH) and `end box' (0AH) characters are used to define teletext boxes. Two start box characters are required to begin a teletext box, with the box starting between the 2 characters. The box ends after an end box character has been encountered.
SAA5288
The display can be set up so that different display modes are invoked inside and outside teletext boxes e.g. text inside boxes but TV outside. This is described in Section 7.6.5. The `normal size' (0CH), `double height' (0DH), `double width' (0EH) and `double size' (0FH) control characters are used to change the size of the characters displayed. If any double height (or double size) characters are displayed on a row the whole of the next row is displayed as spaces. Double height display is not possible on either row 23 or row 24. The character in the position occupied by the right hand half of a double width (or double size) character is ignored, unless it is a control character in which case it takes effect on the next character displayed. This allows double width to be used to produce a display in which blank spaces do not appear when character attributes are changed. The size implying OSD (BCH to BFH) control characters have been included in this device to allow OSD messages to be generated easily. These characters are described in full later in this document.
handbook, halfpage
mosaics character 7FH contiguous
mosaics character 7FH separated
MGL117
Fig.5 Contiguous and separated mosaics.
1997 Jun 24
23
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
7.6.5 DISPLAY MODES
SAA5288
The result of contrast reduction is to improve the readability of the text in a mixed text and video display. The bits in the TXT5 and TXT6 SFRs allow the display to be set up so that, for example, the areas inside teletext boxes will be contrast reduced when a subtitle is being displayed but that the rest of the screen will be displayed as normal video. Setting the shadow TXT4.SHADOW ENABLE bit will add a `south east' shadow to the text, significantly enhancing its readability in mix mode. Shadowing is shown in Fig.6. The readability of text can also be enhanced using `meshing'. Meshing causes the VDS signal to switch so that when the text background colour should be displayed every other pixel is displayed from the video picture. Text foreground pixels are always displayed. The TXT4.BMESH bit enables meshing on areas of the screen within the text display area with black as the background colour. The TXT4.CMESH bit has the same effect on areas with other background colours. Meshing can only be invoked in areas displayed in text mode i.e. where the TXT5.TEXT IN and TXT5.BKGND IN bits are both set to logic 1, and in OSD boxes. Meshed text can also be shadowed. Meshing is illustrated in Fig.6. The TXT4.TRANS bit causes areas of black background colour to become transparent i.e. video is displayed instead of black background. Black background transparency can also only be invoked in areas displayed in text mode i.e. where the TXT5.TEXT IN and TXT5.BKGND IN bits are both set to logic 1, and in OSD boxes.
The device signals the TV's display circuits to display the R, G and B outputs of the device, rather than the video picture, by outputting a logic 1 on the VDS output. The way in which this signal is switched is controlled by the bits in the TXT5 and TXT6 SFRs. There are 3 control functions: text on, background on and picture on. Separate sets of bits are used inside and outside teletext boxes so that different display modes can be invoked. Also, different SFRs are used depending on whether the newsflash (C5) or subtitle (C6) bits in row 25 of the basic page memory are set (SFR TXT6) or not (SFR TXT5). This allows the software to set up the type of display required on newsflash and subtitle pages (e.g. text inside boxes, TV picture outside) this will be invoked without any further software intervention when such a page is acquired. When teletext box control characters are present in the page memory, whichever is relevant of the `Boxes On Row 0', `Boxes On Row 1 - 23' and `Boxes On Row 24' SFR bits in TXT17 must be set if the display mode is to change in the box. These bits are present to allow boxes in certain areas of the screen to be disabled so that teletext boxes can be used for the display of OSD messages without the danger of subtitles in boxes, which may also be in the page memory, being displayed. The use of teletext boxes for OSD messages has been superseded in this device by the OSD box concept, described later, but these bits remain to allow teletext boxes to be used, if required. The COR bits in the TXT5 and TXT6 SFRs control when the COR output of the device is activated (pulled-down). This output is intended to act on the TV's display circuits to reduce the contrast of the video display when it is active. Table 13 Display control bits PICTURE ON 0 0 0 1 1 1 TEXT ON 0 1 1 0 1 1
BACKGROUND ON X 0 1 X 0 1
EFFECT text mode, black screen text mode, background always black text mode TV mode mixed text and TV mode text mode, TV picture outside text area
1997 Jun 24
24
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
SAA5288
normal mix mode handbook, halfpage
SE shadowing
meshing
meshing and shadowing
TV picture text foreground colour
black text background colour
MGL118
Fig.6 Meshing and shadowing.
Table 14 Enhanced display mode selection SHADOW 0 0 0 0 0 0 1 1 1 1 1 TRANS 0 0 0 0 1 1 0 0 0 1 1 BMESH 0 0 1 1 X X 0 1 1 X X CMESH 0 1 0 1 0 1 1 0 1 0 1 DISPLAY normal, unshadowed, unmeshed text text with coloured backgrounds meshed, black background solid text with coloured backgrounds solid, black background meshed text with all backgrounds meshed text with coloured backgrounds solid, black background transparent text with coloured backgrounds meshed, black background transparent shadowed text with coloured backgrounds meshed, black background solid shadowed text with coloured backgrounds solid, black background meshed shadowed text with all backgrounds meshed shadowed text with coloured backgrounds solid, black background transparent shadowed text with coloured backgrounds meshed, black background transparent
1997 Jun 24
25
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
7.7 On Screen Display boxes 7.8 Screen colour
SAA5288
The size implying OSD control characters (BCH to BFH) are intended to allow OSD messages to be displayed. OSD boxes are not the same as teletext boxes created using the teletext boxing control characters (0AH and 0BH). When one of these characters occurs the display size changes appropriately (to normal size for BCH, double height for BDH, double width for BEH and double size for BFH) and an OSD box starts from the next character position (`set after'). The OSD box ends either at the end of the row of text or at the next size implying OSD character. When an OSD box is ended using another size implying OSD character the box ends at the position of the control character (`set at'). This arrangement allows displays to be created without blank spaces at the ends of the OSD boxes. To prevent teletext control characters from affecting the display of the OSD message the flash, teletext box, conceal, separated graphics, twist and hold graphics functions are all reset at the start of an OSD box, as they are at the start of the row. In order to allow the most commonly used display attributes to be set-up before the box starts the foreground colour, background colour and mosaics on/off attributes are not reset. The text within an OSD box is always displayed in text mode i.e. as if the Text On and Bkgnd On bits are both set to a logic 1. The type of display produced inside an OSD box is, therefore, dependant on the states of the TXT4.SHADOW ENABLE, TXT4.TRANS ENABLE, TXT4.BMESH ENABLE and TXT4.CMESH ENABLE register bits, as described previously. OSD boxes can only be displayed in TV mode i.e. when the Picture On SFR bit is a logic 1 and the Text On SFR bit is a logic 0, both inside and outside text boxes and for both normal and newsflash/subtitle pages. The display of OSD boxes is not affected by the C7, suppress header, and C10, inhibit display, control bits stored in row 25 of the page memory.
The register bits TXT17.SCREEN COL2-0 can be used to define a colour to be displayed in place of the TV picture and the black background colour. If the bits are all set to 0, the screen colour is defined as `transparent' and the TV picture and background colour are displayed as normal. Screen colour is displayed from 10.5 to 62.5 s after the active edge of the HSync input and on TV lines 23 to 310 inclusive, for a 625-line display, and lines 17 to 260 inclusive for a 525-line display. When the screen colour has been redefined, no TV picture is displayed so the Frame de-interlace output can be activated, if the SFR bits controlling FRAME are set up to allow this. Table 15 Screen colours SCREEN COL 2 0 0 0 0 1 1 1 1 7.9 Cursor SCREEN COL 1 0 0 1 1 0 0 1 1 SCREEN COL 0 0 1 0 1 0 1 0 1 SCREEN COLOUR transparent red green yellow blue magenta cyan white
If the TXT7.CURSOR ON bit is set, a cursor is displayed. The cursor operates by reversing the background and foreground colours in the character position pointed to by the active row and column bits in the TXT9 and TXT10 SFRs. Setting the TXT9.CURSOR FREEZE bit, causes the cursor to stay in its current position, no matter what happens to the active row and column positions. This means that the software can read data from the memory (e.g. TOP table information) without affecting the position of the cursor.
1997 Jun 24
26
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
7.10 Other display features
SAA5288
The HSync and VSync signals are derived from the signals driving the deflection coils of the TV. Locking the display to the signals from the scan circuits allows the device to give a stable display under almost all signal conditions. The polarity of the input signals which the device is expecting can be set using the TXT1.H polarity and TXT1.V polarity bits. If the polarity bit is a logic 0, a positive going signal is expected and if it is a logic 1, a negative going signal is expected. 7.12 Horizontal timing
Setting the TXT7.DOUBLE HEIGHT bit causes the normal height of all display characters to be doubled and the whole of the display area to be occupied by half of the display rows. Characters normally displayed double height will be displayed quadruple height when this bit is set. Rows 12 to 24 can be enlarged, rather than rows 0 to 11, by setting the TXT7.TOP/BOTTOM bit. This feature can be used for either a user controlled `enlarge' facility or to provide very large characters for the OSD. The display of rows 0 to 23 can be disabled by setting the TXT0.DISPLAY STATUS ROW ONLY bit. The Fastext prompt row (packet 24) can be displayed from the extension packet memory by setting the TXT0.DISPLAY X/24 bit. When this bit is set the data displayed on display row 24 is taken from row 0 in the extension packet memory. When the display from extension packet block option is enabled, the display will revert to row 24 of the basic page memory if bit 3 of the link control byte in packet 27 is set. 7.11 Display timing
Every time an HSync pulse is received the display resynchronizes to its leading edge. To get maximum display stability, the HSync input must have fast edges, free of noise to ensure that there is no uncertainty in the timing of the signal to which the display synchronisation circuits must lock. The display area starts 17.2 s into the line and lasts for 40 s. The display area will be in the centre of the screen if the HSync pulse is aligned with line flyback signal. Therefore, it is better to derive HSync directly from the line flyback or from an output of the line output transformer than from, say, slicing the sandcastle signal as this would introduce delays which would shift the display to the right.
The display synchronises to the device's HSync and VSync inputs. A typical configuration is shown in Fig.7.
handbook, halfpage CVBS
VIDEO DECODING SYNC CIRCUITS
RGB CRT DISPLAY
TUNER/IF HSYNC, VSYNC
RGB, VDS
SAA5288 FRAME
MGL120
Fig.7 Timing configuration.
1997 Jun 24
27
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
7.13 Vertical timing 7.14 Display position
SAA5288
The vertical display timing also resynchronizes to every sync pulse received. This means that the device can produce a stable display on both 625 and 525-line screens. Display starts on the 41st line of each field and continues for 250 lines, or until the end of the field. Normally, television displays are interlaced, i.e. only every other TV line is displayed on each field. It is normal to de-interlace teletext displays to prevent the displayed characters flickering up and down. In many TV designs this is achieved by modulating the vertical deflection current slightly in such a way that odd fields are shifted up and even fields are shifted down on the screen so that lines 1 and 314, 2 and 315 etc. are overlaid. The FRAME output is provided to facilitate this. If the active edge of Vsync occurs in the first half of a TV line this is an even field and the FRAME output should be a logic 0 for this field. Similarly, if VSync is in the second half of the line this is an odd field and FRAME should be a logic 1. The algorithm used to derive FRAME is such that a consistent output will be obtained no matter where the VSync signal is relative to the HSync signal, even if VSync occurs at the start and mid-points of a line. Setting the TXT0.DISABLE FRAME bit forces the FRAME output to a logic 0. Setting the TXT0.AUTO FRAME bit causes the FRAME output to be active when just text is being displayed but to be forced to 0 when any video is being displayed. This allows the de-interlacing function to take place with virtually no software intervention. Some TV architectures do not use the FRAME output but accomplish the de-interlacing function in the vertical deflection IC, under software control, by delaying the start of the scan for one field by half a line, so that lines in this field are moved up by one TV line. In such TVs, VSync may occur in the first half of the line at the start of an odd field and in the second half of the line at the start of an even field. In order to obtain correct de-interlacing in these circumstances, theTXT1.FIELD POLARITY must be set to reverse the assumptions made by the vertical timing circuits on the timing of VSync in each field. The start of the display may be delayed by a line. The `Field Polarity' bit does not affect the FRAME output.
The position of the display relative to the HSync and VSync inputs can be varied over a limited range to allow for optimum TV set-up. The horizontal position is controlled by the X0 and X1 bits in SFR TXT16. Table 16 gives the time from the active edge of the HSync signal to the start of the display area for each setting of X0 and X1. Table 16 Display horizontal position X1 0 0 1 1 X0 0 1 0 1 HSYNC DISPLAY (s) 17.2 16.2 15.2 14.2
The line on which the display area starts depends on whether the display is 625-line or 525-line and on the setting of the Y0 to Y2 bits in SFR TXT16. Table 17 gives the first display line for each setting of Y0 to Y2, for both 625 and 525-line display. On the other field, the display starts on the equivalent line. Table 17 Display vertical position FIRST LINE FOR DISPLAY Y2 0 0 0 0 1 1 1 1 Y1 0 0 1 1 0 0 1 1 Y0 625-LINE 0 1 0 1 0 1 0 1 42 44 46 48 34 36 38 40 525-LINE 28 30 32 34 20 22 24 26
1997 Jun 24
28
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
SAA5288
handbook, full pagewidth
64 s 23 lines 10.5 s X 52 s Y
40 s
25 rows
TEXT DISPLAY AREA
250 lines
287 lines
312 lines
40 characters TV PICTURE AREA FIELD SCANNING AREA
MGL122
Fig.8 625-line display format.
handbook, full pagewidth
63.55 s 17 lines 10.5 s X 52 s Y
40 s
25 rows
TEXT DISPLAY AREA
225 lines
243 lines
263 lines
40 characters TV PICTURE AREA FIELD SCANNING AREA
MGL123
Fig.9 525-line display format.
1997 Jun 24
29
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
7.15 Clock generator
SAA5288
The oscillator circuit is a single-stage inverting amplifier in a Pierce oscillator configuration. The circuitry between OSCIN and OSCOUT is basically an inverter biased to the transfer point. A crystal must be used as the feedback element to complete the oscillator circuitry. It is operated in parallel resonance. OSCIN is the high gain amplifier input and OSCOUT is the output. To drive the device externally OSCIN is driven from an external source and OSCOUT is left open-circuit.
handbook, halfpage
OSCGND
C1
(1)
OSCIN
C2 (1) OSCOUT VSS
MLC110
(1) The values of C1 and C2 depend on the crystal specification: C1 = C2 = 2CL.
Fig.10 Oscillator circuit.
handbook, halfpage
OSCGND VSS external clock OSCIN
not connected
OSCOUT
MLC111
Fig.11 Oscillator circuit driven from external source.
1997 Jun 24
30
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
8 CHARACTER SETS
SAA5288
The two Pan-European character sets are shown in Figs.13 and 14. The character sets for Russian, Greek/Turkish, Arabic/English/French, Thai and Arabic/Hebrew are available on request. 8.1 Pan-European
handbook, full pagewidth
MGL133
Fig.12 Pan-European geographical coverage.
1997 Jun 24
31
E/W = 0
0 0 0 1 1 0 1 0 0 0 1 D E F D E F 0 1 1 0 1 C 1 1 0 1 1 1 B 1 1 1 1 1 1 0 1 0 8 9 A 1 7 7a 6 6a 0 0 1 0 1 0 1 1 5 0 0 1 0 0 4 1 1 1 1 1 1 1 0 1 1 0 1 3 3a 1 0 1 1 0 1 1
E/W = 1
b7
0
0
0
B I T S
b
0
0
0
6 b5
0
0
1
Preliminary specification
SAA5288
Fig.13 Pan-European basic character set.
handbook, full pagewidth
1997 Jun 24
nat opt nat opt OSD OSD background black OSD OSD back ground red OSD OSD background green OSD OSD background yellow OSD OSD background blue OSD OSD background magenta
b
4
0
1
0
b 3 b 2 b1 b 0
r o w
column
0
1
2
2a
Philips Semiconductors
0
0
0
0
0
alpha numerics black
graphics black
0
0
0
1
1
alpha numerics red
graphics red
0
0
1
0
2
alpha numerics green
graphics green
0
0
1
1
3
alpha numerics yellow
graphics yellow
nat opt
0
1
0
0
4
alpha numerics blue
graphics blue
nat opt
0
1
0
1
5
alpha numerics magenta
graphics magenta
TV microcontroller with full screen On Screen Display (OSD)
0
1
1
0
6
alpha numerics cyan OSD OSD background cyan
graphics cyan
0
1
1
1
7
alpha numerics white OSD OSD OSD OSD
graphics white
background white
32
OSD OSD OSD OSD nat opt OSD OSD nat opt nat opt OSD nat opt OSD normal size OSD nat opt nat opt OSD OSD double height OSD nat opt nat opt OSD OSD double width OSD nat opt OSD OSD double size OSD
1
0
0
0
8
flash
conceal display
1
0
0
1
9
steady
contiguous graphics
1
0
1
0
A
end box
separated graphics
1
0
1
1
B
start box
1
1
0
0
C
normal height
black back ground
1
1
0
1
D
double height
new back ground
1
1
1
0
E
double width
hold graphics
1
1
1
1
F
double size
release graphics
MGL124
nat opt
character dependent on the language of page, refer to National Option characters
OSD
customer definable On-Screen Display character
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
SAA5288
handbook, full pagewidth
CHARACTER LANGUAGE E/W C12 C13 C14 ENGLISH(1) 0 0 0 0 23 24 40 5B 5C 5D 5E 5F 60 7B 7C 7D 7E
GERMAN(1)
0
0
0
1
SWEDISH(1)
0
0
1
0
ITALIAN(1)
0
0
1
1
FRENCH(1)
0
1
0
0
SPANISH(1)
0
1
0
1
TURKISH(1)
0
1
1
0
ENGLISH(2)
0
1
1
1
POLISH(1)
1
0
0
0
GERMAN(1)
1
0
0
1
ESTONIAN(1)
1
0
1
0
GERMAN(2)
1
0
1
1
GERMAN(2)
1
1
0
0
SERBO-CROAT(1)
1
1
0
1
CZECH(1)
1
1
1
0
RUMANIAN(1)
1
1
1
1
MGL125
(1) This language conforms to the EBU document SP492 or where superseded ETSI document pr ETS 300 706 with respect to C12/C13/C14 definition. (2) This language is included for backward compatibility with previous generation of Philips teletext decoders.
Fig.14 National option characters.
1997 Jun 24
33
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
8.2 Russian
SAA5288
handbook, full pagewidth
MGL128
Fig.15 Russian geographical coverage.
8.3
Greek/Turkish
handbook, full pagewidth
MGL129
Fig.16 Greek/Turkish geographical coverage.
1997 Jun 24
34
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
8.4 Arabic/English/French
SAA5288
handbook, full pagewidth
MGL131
Fig.17 Arabic/English/French geographical coverage.
8.5
Thai
handbook, full pagewidth
MGL132
Fig.18 Thai geographical coverage.
1997 Jun 24
35
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
8.6 Arabic/Hebrew
SAA5288
dbook, full pagewidth
MGL130
Fig.19 Arabic/Hebrew geographical coverage.
1997 Jun 24
36
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI VO IO IIOK Tamb Tstg Note 1. This value has an absolute maximum of 6.5 V independent of VDD. 10 CHARACTERISTICS VDD = 5 V 10%; VSS = 0 V; Tamb = -20 to +70 C; unless otherwise specified. SYMBOL Supplies VDD IDDM IDDA IDDT supply voltage microcontroller supply current analog supply current display supply current 4.5 - - - 5.0 15 8 15 5.5 30 15 30 PARAMETER CONDITIONS MIN. TYP. PARAMETER supply voltage (all supplies) input voltage (any input) output voltage (any output) output current (each output) DC input or output diode current operating ambient temperature storage temperature note 1 note 1 CONDITIONS MIN. -0.3 -0.3 -0.3 - - -20 -55
SAA5288
MAX. +6.5 VDD + 0.5 VDD + 0.5 10 20 +70 +125 V V V
UNIT
mA mA C C
MAX.
UNIT
V mA mA mA
Digital inputs RESET VIL VIH ILI CI Vth(f) Vth(r) Vhys CI LOW-level input voltage HIGH-level input voltage input leakage current input capacitance VI = 0 to VDD -0.3 0.7VDD -10 - 0.2VDD - - - - - - - - - - 0.2VDD - 0.1 VDD + 0.3 +10 4 - 0.8VDD 4 V V A pF
HSYNC AND VSYNC switching threshold falling switching threshold rising hysteresis voltage input capacitance V V V pF
0.33VDD -
1997 Jun 24
37
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
SYMBOL Digital outputs R, G AND B; note 1 VOL VOH ZO CL IO tr tf VDS VOL VOH CL tr tf LOW-level output voltage HIGH-level output voltage load capacitance output rise time output fall time between 10 and 90%; CL = 50 pF between 90 and 10%; CL = 50 pF IOL = 1.6 mA IOH = -1.6 mA 0 VDD - 0.3 - - - - - - - - 0.2 LOW-level output voltage HIGH-level output voltage output impedance load capacitance DC output current output rise time output fall time between 10 and 90%; CL = 50 pF between 90 and 10%; CL = 50 pF IOL = 2 mA IOH = -2 mA 0 - - - - - - - - - - - 0.2 150 50 -4 20 20 PARAMETER CONDITIONS MIN. TYP.
SAA5288
MAX.
UNIT
V pF mA ns ns
VRGBREF - 0.3 VRGBREF VRGBREF + 0.4 V
V V pF ns ns
VDD + 0.4 50 20 20
R, G, B AND VDS tskew skew delay between any two pins - - 20 ns
COR (OPEN-DRAIN OUTPUT) VOH VOL IOL CL FRAME VOH VOL IOL CL HIGH-level output voltage LOW-level output voltage LOW-level output current load capacitance IOL = 8 mA IOL = -8 mA 0 VDD - 0.5 -8 - - - - - 0.5 VDD +8 100 V V mA pF HIGH-level pull-up output voltage LOW-level output voltage LOW-level output current load capacitance IOL = 2 mA - 0 - - - - - - VDD 0.5 2 25 V V mA pF
1997 Jun 24
38
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
SYMBOL PARAMETER CONDITIONS MIN. TYP.
SAA5288
MAX.
UNIT
Digital input/outputs P0.0 TO P0.4, P0.7, P1.0 TO P1.5, P2.0 TO P2.7 AND P3.0 TO P3.4 VIL VIH CI VOL CL VIL VIH CI VOL CL VIL VIH CI VOL CL tf LOW-level input voltage HIGH-level input voltage input capacitance LOW-level output voltage load capacitance IOL = 3.2 mA -0.3 0.2VDD + 0.9 - 0 - -0.3 0.2VDD + 0.9 - IOL = 10 mA 0 - -0.3 3.0 - IOL = 3 mA between 3 and 1 V 0 - - - - - - - - - - - - - - - - - - 0.2VDD - 0.1 VDD + 0.3 4 0.45 50 0.2VDD - 0.1 VDD + 0.3 4 0.45 50 V V pF V pF
P0.5 AND P0.6 LOW-level input voltage HIGH-level input voltage input capacitance LOW-level output voltage load capacitance V V pF V pF
P1.6 AND P1.7 LOW-level input voltage HIGH-level input voltage input capacitance LOW-level output voltage load capacitance output fall time +1.5 VDD + 0.3 5 0.5 400 200 V V pF V pF ns
Analog inputs IREF Rgnd VI II VIL resistor to ground - -0.3 - -0.3 27 - - - - VDD 12 VDD k
RGBREF; note 1 input voltage DC input current LOW-level input voltage V mA V
ADC0, ADC1 and ADC2 Crystal oscillator OSCIN VIL VIH CI LOW-level input voltage HIGH-level input voltage input capacitance -0.3 0.7VDD - - - - 0.2VDD - 0.1 VDD + 0.3 10 V V pF
1997 Jun 24
39
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
SYMBOL OSCOUT CO fxtal CL C1 C0 Rr Txtal Xj Xd Notes output capacitance - - - Tamb = 25 C Tamb = 25 C Tamb = 25 C Tamb = 25 C - - - -20 - - - 12 32 18.5 4.9 35 +25 - - 10 - - - - - +70 50 x PARAMETER CONDITIONS MIN. TYP.
SAA5288
MAX.
UNIT
pF
CRYSTAL SPECIFICATION; note 2 nominal frequency load capacitance series capacitance parallel capacitance resonance resistance temperature range adjustment tolerance drift MHz pF fF pF C 10-6
30 x 10-6
1. All RGB current is sourced from the RGBREF pin. The maximum effective series resistance between RGBREF and the R, G and B pins is 150 . 2. Crystal order number 4322 143 05561. 11 CHARACTERISTICS FOR THE I2C-BUS INTERFACE SYMBOL SCL timing tHD;STA tLOW tHIGH trC tfC tSU;DAT1 tHD;DAT tSU;STA tSU;STO tBUF trD tfD Notes 1. This parameter is determined by the user software. It must comply with the I2C-bus specification. 2. This value gives the auto-clock pulse length which meets the I2C-bus specification for the special crystal frequency. Alternatively, the SCL pulse must be timed by software. 3. The rise time is determined by the external bus line capacitance and pull-up resistor. It must be less than 1 s. 4. The maximum capacitance on bus lines SDA and SCL is 400 pF. 1997 Jun 24 40 START condition hold time SCL LOW time SCL HIGH time SCL rise time SCL fall time 4.0 s 4.7 s 4.0 s 1.0 s 0.3 s 250 ns 0 ns 4.7 s 4.0 s 4.7 s 1.0 s 0.3 s note 1 note 1 4.0 s; note 2 note 3 0.3 s; note 4 4.0 s 4.7 s 4.0 s 1.0 s 0.3 s 250 ns 0 ns 4.7 s 4.0 s 4.7 s 1.0 s 0.3 s PARAMETER INPUT OUTPUT I2C-BUS SPECIFICATION
SDA timing data set-up time data hold time repeated START set-up time STOP condition set-up time bus free time SDA rise time SDA fall time note 1 note 1 note 1 note 1 note 1 note 3 0.3 s; note 4
Preliminary specification
SAA5288
Fig.20 I2C-bus interface timing.
handbook, full pagewidth
1997 Jun 24
repeated START condition START condition STOP condition t rD t SU;STA 0.7V DD 0.3VDD t fC t BUF t SU;STO 0.7VDD 0.3VDD t SU;DAT3 t SU;DAT2
MLC104
Philips Semiconductors
START or repeated START condition
SDA (input / output)
TV microcontroller with full screen On Screen Display (OSD)
t fD
t rC
41
t HIGH t SU;DAT1 t HD;DAT
SCL (input / output)
t HD;STA
t LOW
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
12 QUALITY SPECIFICATIONS
SAA5288
This device will meet Philips Semiconductors General Quality Specification for Business group "Consumer Integrated Circuits SNW-FQ-611-Part E"; "Quality Reference Handbook, order number 9398 510 63011". The principal requirements are shown in Tables 18 to 20. Table 18 Acceptance tests per lot; note 1 TEST Mechanical Electrical cumulative target: <80 ppm cumulative target: <80 ppm REQUIREMENTS
Table 19 Processability tests (by package family); note 2 TEST solderability mechanical <7% LTPD <15% LTPD REQUIREMENTS
solder heat resistance <15% LTPD Table 20 Reliability tests (by process family); note 3 TEST operational life humidity life temperature cycling performance 168 hours at Tj = 150 C temperature, humidity, bias 1000 hours, 85 C, 85% RH (or equivalent test) Tstg(min) to Tstg(max) CONDITIONS REQUIREMENTS <1000 FPM at Tj = 70 C <2000 FPM <2000 FPM
Table 21 Reliability tests (by device type) TEST ESD and latch-up CONDITIONS ESD Human body model 100 pF, 1.5 k ESD Machine model 200 pF, 0 latch-up Notes to Table 16 to 18 1. ppm = fraction of defective devices, in parts per million. 2. LTPD = Lot Tolerance Percent Defective. 3. FPM = fraction of devices failing at test condition, in Failures Per Million. 2000 V 200 V 100 mA, 1.5 x VDD (absolute maximum) REQUIREMENTS
1997 Jun 24
42
40 V A0 RC SCL SDA VDD VDD A1
VDD
VDD
ndbook, full pagewidth
1997 Jun 24
VDD 47 F 100 nF VSS VSS VSS P2.0/TPWM 1 52 51 50 49 48 47 46 45 44 43 42 41 40 OSCGND VDDD VDDA VSYNC HSYNC VDS R G B RGBREF 31 30 29 28 27 P3.4/PWM7 COR VSSD FRAME 26 VSS
MGL126
Vtune VDD VSS A2
PH2369
EEPROM PCF8582E
VSS VSS
Philips Semiconductors
VDD P1.5 P1.4 P1.7/SDA P1.6/SCL P1.3/T1 P1.2/INT0 P1.1/T0 P1.0/INT1 VDDM RESET XTALOUT XTALIN 22 pF VDD 47 F 12 MHz VDD 100 nF VSS field flyback line flyback 2.2 F VDD VDD IR RECEIVER TV control signals
brightness 2 3 4 5 6 7 8 9 10 11 12 13 P2.2/PWM1 P2.3/PWM2 P2.4/PWM3 P2.5/PWM4 P2.6/PWM5 P2.7/PWM6 VSS P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 VSSD VSS P0.0 14 39 38 37 36 35 34 33 32 15 16 17 18 19 20 21 22 23 24 25 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 1 k VSSD VSS i.c. i.c. i.c. IREF 27 k VSS
P2.1/PWM0
contrast
13 APPLICATION INFORMATION
saturation
hue
volume (L)
volume (R)
TV microcontroller with full screen On Screen Display (OSD)
VAFC
VDD
43
SAA5288
VSS
VSS
VDD
VDD
to TV's display circuits
Preliminary specification
SAA5288
Fig.21 Application diagram.
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
14 EMC GUIDELINES If possible, a ground plane under the whole IC should be present, i.e. no signal tracks running underneath the IC as shown in Fig.22. The ground plane under the IC should be connected by the widest possible connection back to the ground connection of the PCB, and electrolytic decoupling capacitor. It should preferably not connect to other grounds on the way and no wire links should be present in this connection. The use of wire links increases ground bounce by introducing inductance into the ground, thereby reducing the electrolytic capacitor's decoupling efficiency. The supply pins should be decoupled at the pin, to the ground plane under the IC. This is easily accomplished when using SM capacitors (which are also most effective at high frequencies).
SAA5288
Each supply pin should be connected separately to the power connection of the PCB, preferably via at least one wire link which: 1. May be replaced by a ferrite or inductor at a later point if necessary 2. Will introduce a small amount of inductance. Signals connected to the +5 V supply e.g. via pull-up resistors, should be connected to the +5 V supply before the wire link to the IC (i.e. not the IC side). This will prevent if from being polluted and conduct or radiate noise onto signal lines, which may then radiate themselves. OSCGND should connect only to the crystal load capacitors (and not GND).
handbook, full pagewidth
GND +5 V
electrolytic decoupling capacitor (2 F)
wire links other GND connections SM decoupling capacitors (10 to 100 nF) VDDM VDDD VDDA
under-IC GND plane GND connection note: no wire links
under-IC GND plane
VSSD
IC VSSA
MGL127
Fig.22 Power supply and GND connections for SOT247-1.
1997 Jun 24
44
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
15 PACKAGE OUTLINE SDIP52: plastic shrink dual in-line package; 52 leads (600 mil)
SAA5288
SOT247-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 wM (e 1) MH b 52 27
pin 1 index E
1
26
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 5.08 A1 min. 0.51 A2 max. 4.0 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 47.9 47.1 E (1) 14.0 13.7 e 1.778 e1 15.24 L 3.2 2.8 ME 15.80 15.24 MH 17.15 15.90 w 0.18 Z (1) max. 1.73
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT247-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 90-01-22 95-03-11
1997 Jun 24
45
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
16 SOLDERING 16.1 Introduction
SAA5288
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 16.2 Soldering by dipping or by wave
The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 16.3 Repairing soldered joints
Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
1997 Jun 24
46
Philips Semiconductors
Preliminary specification
TV microcontroller with full screen On Screen Display (OSD)
17 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA5288
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 18 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 19 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1997 Jun 24
47
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547047/00/01/pp48
Date of release: 1997 Jun 24
Document order number:
9397 750 01856

▲Up To Search▲

Price & Availability of SAA5288

	To Download SAA5288 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .